I applied through a recruiter. I interviewed at Tessolve (Bengaluru)
Interview
two technical round followed by hr . they are more checking my sv , uvm knowledge and current project contribution. based on scenario we have to explain the uvm tb creation and verification clousure
Interview process was very good . The questions was basically based on Verilog and system Verilog. Also some aptitude questions. It was good and very easy. If we study basic verilog questions then we will be able to perform the interview very well
I applied through an employee referral. I interviewed at Tessolve in Jan 2020
Interview
One technical round followed by one HR round. Both were face to face interview. Each round lasted an hour each. For senior design engineers, there will be another round of technical interview
Interview questions [1]
Question 1
Op-amp design, band gap reference, previous projects and basic MOSFET questions