General Interview process.
4 phn rounds with the team and then 6 on-site interviews.
The questions were on projects mentioned on resume,asic flow , CMOS design, and logic design.
Interviewers were friendly, made me confortable to answer everything.
Interview questions [1]
Question 1
There are two blocks, in the left block (block A) there were 2 FF, FFa and FFb. in block B there were only logic. FFa routed through logic to block B, and returned through logic to FFb in Block A. there is 150ns delay in the timing path between FFa and FFb,what can be the cause and how to fix it.