Internal Transfer within Intel 2 phone/video interviews (manager and team member) Each 90 minutes Interview details - discussion about experience with relation to pre silicon verification (test bench development using System-Verilog and UVM) Basic questions relating to UVM basics (components, test phases, agents, interfaces, checkers, monitors, sequences) and System-Verilog (classes, tasks, functions, constraints)

Coding related questions Project questions Logical questions Resume go through Sv uvm que Overall good experience working in intel Good company to work Constraint que, driver , monitor, scoreboard que