It was a smooth process, mostly technical problems, no tricky questions. Mostly asked about previous project on resume, with some coding questions at the end. Total 4hr with 4 different engineer/manager
The interview process consisted of two rounds. The first was a technical screen focusing on Verilog and RTL design. The second was a behavioral interview with the manager. nice processes overview
I applied through an employee referral. I interviewed at Synopsys in Mar 2025
Interview
hard. fifo's n all. and other designing questions. muxes, gates, cdc n all. designing n other implementation questions are their . tough questions were their. U get designing to the best.
Interview questions [1]
Question 1
ok. fifo..design n implementation.and other designing questions
