Silicon Labs interview questions

It was 3 rounds of interviews, and I got rejected after second. First was recruiter call and second was with a hiring manager, both were conversational and respectful. Third one is supposed to be a technical round in person.

45 minutes long. Asked about projects on resume, then had to debug some wrong Verilog code, and fix it. Asked about experience in Verilog, SystemVerilog, and debugging. Especially verification, ask how you used verification in previous work.