Recently applied for a Physical Design (PD) role ...through a referral,
The focus was largely on fundamentals and real project exposure rather than just theory. A few core areas that were discussed:
Basics of PD flow – synthesis → floorplanning → placement → CTS → routing → signoff
Understanding of timing concepts – setup/hold, slack, clock skew, timing closure strategies
Questions around floorplanning decisions – macro placement, congestion handling
Clock Tree Synthesis (CTS) – how to balance skew and latency
Routing challenges – congestion, DRC/LVS issues, and fixes
Power planning – IR drop, EM, and mitigation techniques
Debug scenarios – “What would you do if timing is not closing?” or “How do you handle congestion in a block?”
They also touched upon:
Tools exposure (Synopsys/Cadence)
Real-time problem-solving scenarios
Trade-offs between performance, power, and area (PPA)
