Qualcomm System Level Test Engineer interview questions

Round 1 was heavily focused on: Yield analysis Determinism vs marginal silicon Production screening mindset Business impact & customer risk PVT and SLT prioritization Round 2 focused on: Embedded fundamentals Automation architecture Python & OOP Concurrency Debugging mindset Hardware-software interaction This are some of the questions which I remember You have 1 million chips and 50,000 fail the same CPU test case. Is it a test gap or silicon problem? If 50k fail and after retest half pass, what does that indicate? If a chip fails 2 out of 3 times, should we ship it to the customer? Who manufactures the chips? Are chips on the same wafer exactly identical? Is it possible some chips are completely bad and some are good? What can wafer sort catch? Why can’t wafer sort replace SLT? What is ADB? To what extent do you know ADB? What are core IPs in an SoC? What is IP? What type of test cases did you design? What challenges did you face? Explain SPI protocol. When would you choose UART vs SPI vs I2C? Describe the normal boot process and major milestones. What other lab equipment have you used besides oscilloscope?