Process was good. Started with basic questions and then covered entire verification flow. Some basic questions on verilog, system verilog, UVM.
Questions related to your previous project. DIfferent types of FSM and differences.
Interview questions [1]
Question 1
FSM for sequence detector.
Verification environment.
Verilog programming.
I applied through other source. The process took 2 days. I interviewed at Qualcomm (Bengaluru) in Apr 2024
Interview
The Interview was setup for 3 hours.
One person took interview for ~1 hour and then the other person for 1 hour and the interview is done.
They asked me about my past experience and past projects.
They asked me what are my strong subjects and started interview on the same.
Interview questions [1]
Question 1
What is deep copy and shallow copy in System Verilog?
Can you tell about sequencer in UVM and what is the use of it?
What is virtual interface and why it is used?
Gave a Constraint and asked what will be the randomised values.
Asked to write an assertion for a given scenario
Asked to write a constraint such that it will generate even and odd numbers in sequence.
I applied through an employee referral. I interviewed at Qualcomm (Bengaluru) in Jun 2021
Interview
The interview process was smooth had 5 hrs of process and it went very well they have asked all the previous experience and all the sv UVM related main topics
