Allegro MicroSystems Design Engineer interview questions

Round 1: verilog vs SV, latch vs flip flop, left shift and right shift, sensitivity list, number of address bits required for storing 512KB of memory, why nmos is faster, why pmos is bigger in size, some question on resistance Round 2: I solved these and shared answers with the recruiter. not very usual 1. 2 bit comparator with each bit 2bits and draw a gate level sim for a<b, a>b, a=b 2. 11011 seq detector 3. Why did you choose mealy/Moore for question 2 4. was given cmos inverter circuit and was asked to describe the different regions. 5. Was given a nmos-pmos circuit and was asked if this was valid Round 3: 1. syn reset vs asyn set, which has higher priority, write the verilog code. 2. full adder and half adder 3.setup time hold time were given and was asked the timing for the seq+comb circuit(I messed up this one)