I applied through a recruiter. I interviewed at Apple (San Jose, CA)
Interview
HR contacted and scheduled an Interview with a hiring manager. It took around 2 weeks to get a call for the interview.
Interview questions:
- SystemVerilog assertion and constraints
- UVM phase question
Interview questions [1]
Question 1
Q. What are all run-phases and in detail discussion about it
Q. Basic constraints related to dist, and assertion
There were 1 screening and 6 panel rounds and it was difficult especially UVM part also they AMBA protocols basic design questions like fsm fifo and all and more focus on constraints
Interview questions [1]
Question 1
UVM based questions and Assertions and constraints
I applied online. I interviewed at Apple (Sunnyvale, CA) in Mar 2026
Interview
I had a screening round that started directly without any introduction. I was asked questions about my resume, mainly about my projects. After that, I was given a coding question.
first asking about the tool experience, asking about UVM knowledge like how and when to connect the sequencer and driver and what is their handshake , how do you deal with CDC problems, how to do the STA analysis, then final having a coding question
Interview questions [1]
Question 1
implementation of driver class based on the figure they gave